Translation Lookaside Buffer: a small piece of associative memory within a processor which caches part of the translation from virtual addresses to physical addresses. Such translations can often be very large and complex and the data structures that implement them too large to store efficiently on the processor. Instead, a few elements of the translation are stored in the TLB, which the processor can access extremely quickly. If a required translation for a particular virtual address is not present in the TLB the address will be resolved using the more general mechanism. Also referred to as Address Translation Cache.
translation lookaside buffer. for a paging system, a high-speed hardware lookup table for the conversion of virtual addresses generated by the processor into real addresses. The table is of limited size and only holds recently used page addresses. [SILC99
(n.) translation look-aside buffer; the memory cache of the most recently used page table entries within the memory management unit.
Translation Lookaside Buffer. A hardware unit that serves as a cache for virtual-to-absolute memory address mapping.
Translation Lookaside Buffer. A hardware structure in each processor of the V-Class server that contains the information necessary to translate a virtual memory reference to a physical page and to validate memory accesses.
See translation look-aside buffer.
Translation look-aside buffer. The translation look-aside buffer (TLB) is a table in the processor that contains cross-references between the virtual and real addresses of recently referenced pages of memory.
A table used in a virtual memory system that lists the physical address page number in association with each virtual address page number. A TLB is used in conjunction with a cache whose tags are based on virtual addresses. The virtual address is presented simultaneously with the TLB and with the cache so that cache access and the virtual-to-physical address translation can proceed in parallel (the translation is done "on the side"). If the requested address is not cached, the physical address is used to locate the data in main memory. The alternative would be to place the translation table between the cache and main memory so that it would only be activated when a cache miss occurred.
translation lookaside buffer. A table within the CPU that associates virtual addresses to physical page addresses. The TLB has limited size, but all entries are searched in parallel, simultaneously with the decoding of the instruction (hence "lookaside"). When the operand address of an instruction is found in the TLB, the CPU can present the needed physical address to the memory without delay. (The TLB is in essence a cache for page table entries.) When the TLB lookup fails, the CPU traps to an OS routine that locates the desired virtual page in a large, in-memory page table that defines the virtual address space of the process. When that lookup succeeds, the OS loads one entry of the TLB to address the page, and resumes execution. When that lookup fails, the process has suffered a page fault.
Translation Look-aside Buffer. A specialised cache that holds a table of physical addresses as generated from the virtual addresses used in the program code.
Translation lookaside buffer. An on-chip cache that stores recently used mappings between real and virtual memory. The Itanium architecture has separate TLBs for instructions and data.
