Constraints are specifications for the implementation process. There are several categories of constraints: routing, timing, area, mapping, and placement constraints. Using attributes, you can force the placement of logic (macros) in CLBs, the location of CLBs on the chip, and the maximum delay between flip-flops. PAR does not attempt to change the location of constrained logic. CLBs are arranged in columns and rows on the FPGA device. The goal is to place logic in columns on the device to attain the best possible placement from the point of view of performance and space.
Bounding conditions governing aspects of the implementation of planetary protection requirements.
(More commonly described as "environmental features.") Significant resources, facilities, or other features of a study area located in or adjacent to an existing or proposed corridor study area that serve to restrain, restrict, or prevent the ready implementation of proposed transportation improvements in a given area; may include natural or physical resources, important structures, communities facilities, or topographic features.