This term describes a processor that is capable of executing more than one instruction during a processor cycle. Processors can do this by fetching multiple instructions in one cycle, deciding which instructions are independent of other instructions, and executing them.
A CPU architecture that allows more than one instruction to be executed in one clock cycle. Processors can do this by fetching multiple instructions in one cycle, deciding which instructions are independent of other instructions, and executing them.
Of a computer processor, being able to schedule operations for side-by-side execution. Typically, a superscalar processor can schedule an integer operation, a floating point operation and a memory operation for simultaneous execution in different pieces of hardware. Superscalar chips also make heavy use of pipelining.
A second generation RISC designed for an optimal balance between compiler and machine instructions.
A superscalar CPU can execute more than one instruction per clock cycle. B...
In a RISC CPU, the ability to execute more than one instruction per clock cycle, achieved by having multiple parallel execution units. The MIPS R10000 CPU routinely achieves instruction rates of 1.5 to 2 times its clock rate. It uses five, independent execution units, and is able to execute instructions out of order, so that it can complete some instructions while waiting for the memory operands of others to arrive. See also speculative execution and software pipelining.
Hardware designs that makes possible the simultaneous processing of multiple instructions.
A type of microprocessor design incorporating multiple functional units together with sufficient hardware complexity to allow units to function relatively autonomously. This type of design provides opportunities for concurrent operations to take place during a single clock cycle.
A superscalar CPU architecture implements a form of parallelism called Instruction-level parallelism within a single processor. It thereby allows faster CPU throughput than would otherwise be possible at the same clock rate. A superscalar architecture executes more than one instruction during a single pipeline stage by pre-fetching multiple instructions and simultaneously dispatching them to redundant functional units on the processor.