(v.) to fetch or load a data entity or program instruction from memory in advance of actually starting to process it. Processors that have prefetch instructions can avoid some of the bottlenecks that arise from a memory system that is slower than processing speed.
An instruction that notifies the CPU that a particular cache line will be needed by a following instruction, permitting memory fetch to overlap execution. The prefetch instruction is simply a load that does not use its operand. Current Silicon Graphics compilers can generate prefetch instructions automatically.
In DDR1 SDRAM, every I/O buffer can output two bits per clock cycle. These two bits are fetched from the memory array (or prefetched) before being released to the DQ (data queue) output. DDR2 SDRAM has a four bit prefetch. The DQ outputs the data in a time multiplexed manner.